1. Field of the Invention
The present invention relates to a semiconductor device having a structure in which part of a semiconductor substrate is isolated via an insulating layer. Moreover, the present invention relates to a method of manufacturing the semiconductor device.
2. Description of the Related Art
The performance of semiconductor elements used in Si-LSIs, in particular, MOSFETs has been enhanced year by year with advances in LSI technology. However, a limit to the lithography technique is indicated in light of recent process techniques, while saturation of mobility is indicated in light of element physics. For this reason, it is very difficult to achieve high performance of the semiconductor elements.
The following technique has attracted special interest as a method of improving electron mobility, which is one of the high-performance indices of an Si-MOSFET. According to the technique, strain is applied to an active layer for forming elements. The strain is applied to the active layer, and thereby, the band structure changes and carriers contained in a channel are prevented from scattering. Thus, it is expected to enhance the mobility. More specifically, a compound crystal layer consisting of a material having a lattice constant larger than silicon (Si) is formed on an Si substrate. For example, a strain-relaxed SiGe compound crystal layer (hereinafter, referred simply to as SiGe layer) having 20% Ge concentration is formed on the Si substrate. When an Si layer is formed on the SiGe layer, a strained Si layer to which strain is applied is formed according to the difference in the lattice constant. The following report has been made (e.g., see J. Welser, J. L. Hoyt, S. Takagi and J. F. Gibbons, IEDM 94-373). According to the report, when the strained Si layer is used as a channel of the semiconductor device, it is possible to obtain electron mobility of about 1.76 times as much as the case where a non strained Si channel is used.
In order to form the foregoing strained Si channel on an silicon-on-insulator (SOI) structure, the present inventors realized a device structure using the following method. According to the method, the strained Si layer is formed on the strain-relaxed SiGe layer on a buried oxide layer (e.g., see T. Mizuno et al., 11-3, 2002 Symposia on VLSI Tech.). A transistor having such a structure is excellent in short channel effect (SCE) and reduction of parasitic capacitance; therefore, it serves to realize high-performance elements.
However, if the scale-down further advances, for example, a 35 nm node element will be produced in future. In this case, the thickness of the strained Si channel is experimentally ⅓ to ¼ of the gate length, that is, several nanometers, and thus, becomes extremely thin. For this reason, there is a possibility that the crystal layer deteriorates. For example, if the strained Si layer is given as one example, the lattice spacing between a front-end layer and a back-end strain-applied layer is percent (%) order to apply strain. As a result, crystal defect resulting from strain occurs in crystal.
If the strained Si channel contacts with a semiconductor material different from Si, for example, front-end SiGe layer, there is a possibility that Ge diffuses from the SiGe layer to the strained Si layer. This is a factor of causing a strain change, carrier transportation change or increase of interface state in the element producing process and in the device operation. For this reason, there is a possibility that element characteristics are degraded.
Meanwhile, one-chip technique development, typical of DRAM embedded process, is important as a technique required for manufacturing logic operation elements applied to a next generation computer system. The foregoing embedded process has attracted special interest for the following reason. Because, the embedded process is a technique of forming a logic circuit and a memory elements such as DRAM on the same substrate, and reducing power consumption and cost while maintaining high speed operation. In this case, high performance elements having high processing speed are required as the logic circuit. On the other hand, high-quality semiconductor devices must be manufactured in view of yield to form the memory elements.
In the technique of integrating high-performance logic element and high-quality memory element on the same substrate, it is necessary to break down a limit of high-performance logic element resulting from a limit of scale-down. In addition, there is a limit in the method of integrating high-quality memory elements on the single substrate like the conventional technique. Moreover, the following various problems are mixed; as a result, there is a problem that it is more and more difficult to achieve integration between generations. The various problems are as follows.
Reduction of element performance enhancement effect resulting from the advance of scale-down
Cost Increase
Increase of the number of manufacturing processes
Difficulty of circuit design by drive force reduction resulting from high integration
Consequently, it is necessary to realize the technique of integrating logic elements requiring higher performance and memory elements requiring higher quality and higher integration on the same substrate. It has been desired to realize a semiconductor device which is adaptable to reduction of cost and number of processes, and to realize a method of manufacturing the semiconductor device.